One caution must be mentioned with regard to the use of the 6502 instruction set. Every computer language has its own syntax, the way each command must be written for the computer to understand it. Different assemblers for the ATARI require slightly different syntax, described in detail in Chapter 6.

In this Appendix, we shall learn the commands which the 6502 can execute. The complete set of commands for the 6502 is generally referred to as the 6502 instruction set. Here the instructions are described in alphabetical order for easy reference. Along with each instruction you will find:
1. Examples of its use
2. Descriptions of the various addressing modes available for that instruction (see Chapter 5)
3. The effect of each instruction upon the various flags in the processor status register (see Chapter 3)

THE INSTRUCTION

As discussed in Chapter 4, each instruction for the 6502 is abbreviated into a three-letter code called a mnemonic. The first instruction, Add with Carry, is the only instruction available for carrying out addition of two numbers. Here's an example of its use:

…     ; these represent
…     ; some previous
…     ; instructions

Let's examine what happens when we execute this instruction. The 6502 takes whatever is already contained in the accumulator and adds to it the decimal number 2. The resulting sum remains in the accumulator, awaiting further instructions. However, there is a complication. Remember, the name of this instruction is Add with Carry. What about the carry? Remember that the Carry bit is one of the flags in the processor status register. Whenever the ADC instruction is encountered, the Carry bit is added to the sum in the accumulator. Let's suppose that just before encountering this instruction, we had stored a zero in the accumulator, and the Carry bit was a zero, as well. The sum stored in the accumulator following the execution of this instruction would still be 2, as described. However, if the Carry bit had been a 1, then the sum would have been 3. Schematically, this addition is as follows:

Accumulator  Carry Bit  Instruction    = >  Sum  Carry Bit
0                   0          ADC #2     = >     2            0
0                   1          ADC #2     = >     3            0

Note that if the Carry bit is initially 1, it is reset to zero after the ADC instruction is executed. This makes sense, since we've already used the carry. If it wasn't reset to zero by the 6502, we might use the Carry bit twice without realizing it.

EFFECTS ON THE PROCESSOR STATUS REGISTER

The 6502 also sets the Carry bit appropriately, as in the following examples:

Accumulator  Carry Bit  Instruction    = >  Sum  Carry Bit
253                  0          ADC #6     = >     3            1
253                  1          ADC #6     = >     4            1

In the first example, 253 + 6 = 259, but we know that the largest number the accumulator can hold is 255. The number 256 represents zero, with a carry of one, so 259 is 3 with a carry of 1. The number 3 is stored in the accumulator and the Carry bit is set.

In the second example, the Carry bit starts at 1, so when it is added into the sum, the sum is 4. Remember, after the Carry bit is used, the 6502 resets it to zero. So why does example 2 end up with the Carry bit set? The sum was greater than 255, so the Carry bit was set before execution of the instruction was completed.

We have already discussed the ability of the 6502 to operate in decimal mode. Note here that the largest number the accumulator can store in decimal mode is 99. The Carry bit is set following an ADC instruction in decimal mode if the sum exceeds 99.

Several other flags in the processor status register are also conditioned by the ADC instruction. The Overflow bit, V, is set when bit 7, the most significant bit, is changed because of the addition. The Negative flag, N, is set if the addition produces a number greater than 127; that is, when the most significant bit, bit 7, is a 1. Remember, to the 6502, any number between 128 and 255 is a negative number, because its most significant bit is a 1. Finally, the Zero flag, Z, is set if the result of the addition is zero. Some examples of these conditions are shown below:

 A  N  Z  C  V Instruction = > A  N  Z  C  V Comments 2   0   0   0   0 ADC #3 = > 5   0   0   0   0 Straight addition 2   0   0   1   0 ADC #3 = > 6   0   0   0   0 Remember: add the carry! 2   0   0   0   0 ADC #254 = > 0   0   0   0   0 C and Z flags set 2   0   0   0   0 ADC #253 = > 255 1   0   0   0 N and V flags set 253 1   0   0   0 ADC #6 = > 3   0   0   1   1 C and V set; N reset 125 0   0   1   0 ADC #2 = > 128 1   0   0   1 N and V set; C reset

It should now be apparent that by testing the various flags, we can easily obtain a great deal of information about the results of an addition. Instructions for testing these flags are provided and are used frequently in most assembly language programs.

The ADC instruction allows any of the same eight addressing modes discussed in Chapter 5 for the LDA instruction. They are illustrated below, with the number of cycles and bytes used for each instruction:

 Mode Instruction Cycles Bytes Meaning Immediate ADC #2 2 2 A + #2 Absolute ADC \$3420 4 3 A + contents of memory \$3420 Zero Page ADC \$F6 3 2 A + contents of memory \$F6 Zero Page,X ADC \$F6,X 4 2 A + contents of memory \$F6 + X Absolute,X ADC \$3420,X 4 3 A + contents of memory \$3420 + X Absolute,Y ADC \$3420,Y 4 3 A + contents of memory \$3420 + Y Indexed Indirect ADC (\$F6,X) 6 2 A + contents of address at \$F6+ X Indirect Indexed ADC (\$F6),Y 5 2 A + contents of (address at \$F6) + offset Y

For more complete explanations of these addressing modes, please see Chapter 5.

AND The Logical AND Instruction

THE INSTRUCTION

The AND instruction performs a logical AND of the accumulator and the operand. A logical AND takes two numbers and compares them bit for bit. For each bit, if both numbers being compared contain a 1, the result contains a 1 as well; if either number contains a zero, the result contains a zero in that bit. Let's look at an example in which the accumulator contains the number 5:

AND #\$0E

The easiest way to visualize the AND operation is to convert each of the two numbers being compared to binary nomenclature, as follows:

Hex.             Binary
#5 = #%00000101
#\$0E = #%00001110
result = #%00000100  =  #4

We can easily see that the only bits set to 1 in the result are those in which both numbers being compared have a 1, in this example, bit 2. Let's try another example. The accumulator contains 147, and this is the instruction:

AND #\$1D

As above, we convert to binary:

#147  =  #%10010011
#\$1D =  #%00011101
result  =  #%00010001  =  #17

This fairly straightforward instruction is used frequently, so you should now try an exercise by yourself. We'll assume the accumulator contains the number #\$BC, and this is the instruction:

AND #234

See if you can work out the answer for yourself.

The AND instruction is used to mask a byte in a specific way. For instance, suppose you want to know the value of the low nibble of a number. To find out, you simply AND the number with #\$0F Since the high nibble of this number is zero and the low nibble is all ones, the result will be equal to the low nibble of the number you started with. Similarly, to obtain the high nibble you only have to AND with #\$F0. Now let's present the answer to the above problem:

#\$BC = #%10111100
#234  = #%11101010
result  = #%10101000  =  #168

EFFECTS ON THE PROCESSOR STATUS REGISTER

The AND instruction sets the Zero flag if the result is equal to zero, or resets the Zero flag if the result is not equal to zero. This instruction also sets the Negative flag if the result is greater than 127, or resets this flag if the result is less than 128. Several examples of this follow:

 A Z N Instruction = > A Z N Meaning #5 0 0 AND #8 = > 0 1 0 Z set by result = 0 #\$FE 0 1 AND #\$5F = > #\$5E 0 0 N reset by result< 127

The AND instruction can also be written in any of the same eight addressing modes discussed in Chapter 5 for the LDA instruction.

 Mode Instruction Cycles Bytes Meaning Immediate AND #2 2 2 A & #2 Absolute AND \$3420 4 3 A & contents of memory \$3420 Zero Page AND \$F6 3 2 A & contents of memory \$F6 Zero Page,X AND \$F6,X 4 2 A & contents of memory \$F6 + X Absolute,X AND \$3420,X 4 3 A & contents of memory \$3420 + X Absolute,Y AND \$3420,Y 4 3 A & contents of memory \$3420 + Y Indexed Indirect AND (\$F6,X) 6 2 A & contents of address at \$F6 + X Indirect Indexed AND (\$F6),Y 5 2 A & contents of (address at \$F6) + offset Y

ASL Arithmetic Shift Left

THE INSTRUCTION

The ASL instruction utilizes the carry bit in the processor status register as a ninth bit for a number, and pushes each bit in a number one place to the left; thus, the name arithmetic shift left. A zero is pushed into the least significant bit, and the most significant bit of the original number ends up in the Carry bit. A picture is worth a thousand words here:

C         76543210
0  < =  10110101    < =  0
1          01101010

Let's look at another example:

C         76543210
0  < =  01101101  < =  0
0          11011010

"What is the purpose of this instruction?" you may ask. Well, let's look more closely at the last example. The original number, #%01101101, is #109 in decimal form; following the ASL the resulting number is #%11011010, which is #218 in decimal form. We have doubled the number with a single instruction! Since each position in a binary number is exactly twice the value of the position to its immediate right, a shift to the left doubles the value of each bit. This is an extremely easy way of multiplying numbers by powers of 2; just ASL once for each power of 2 required.

CAUTION:    Although it seems fairly easy to multiply a number by 2 using the ASL instruction, you must be extremely careful and correct for overflow into the Carry bit. An example of this is the first set of numbers above. We started with #%10110101, which is the decimal number 181, and following our ASL we had #%01101010, which is the decimal number 106. Now we know that 106 is not 2 times 181. In fact, 2 times 181 is 362. Note that this is exactly 106, the result we got, plus 256. Remember, in that example, we concluded with a carry of 1, which represents 256 when using the ASL instruction for multiplication. You must take this carry into account whenever you use the ASL instruction.

EFFECTS ON THE PROCESSOR STATUS REGISTER

As we have already seen, the Carry bit will contain the most significant bit of the original number. The Negative flag will be set equal to the most significant bit of the result (bit 6 of the original number). The Zero flag will be set if the result is equal to zero, and will be reset for any other result. In the examples shown below, we'll use the accumulator addressing mode.

 A N C Z Instruction = > A N C Z #128 1 0 0 ASL A = > #0 0 1 1 #64 0 0 0 ASL A = > #128 1 0 0 #192 1 0 0 ASL A = > #128 1 1 0 #8 0 0 0 ASL A = > #16 0 0 0

Examples using the five addressing modes for the ASL instruction are listed below:

 Mode Instruction Cycles Bytes Meaning Accumulator ASL A 2 1 ASL value in accumulator Absolute ASL \$3420 6 3 ASL contents of memory \$3420 Zero Page ASL \$F6 5 2 ASL contents of memory \$F6 Zero Page,X ASL \$F6,X 6 2 ASL contents of memory \$F6 + X Absolute,X ASL \$3420,X 7 3 ASL contents of memory \$3420 + X

Note that this instruction takes quite a while to execute. In fact, the Absolute,X addressing mode of the ASL instruction requires 7 machine cycles to execute, the longest of any of the instructions in the entire 6502 set. However, we need to think about speed in absolute terms. Using this instruction allows us to perform a multiplication by 2 in 3.92 microseconds, even in this slowest of modes. Still pretty fast, especially when compared with BASIC!

BCC Branch on Carry Clear

THE INSTRUCTION

In BASIC, we can distinguish between two different types of commands which both transfer the control of a program to a new line number. The first is the straight GOTO command; we know that the number of the next line to be executed will always follow the command GOTO:

45 GOTO 90
50 .
60 .
90 ? "This line follows 45."

After line 45 is executed, line 90 is the next line under all conditions. This is called an unconditional transfer of control.

A second type of transfer in BASIC utilizes the comparison and branching abilities of the computer:

45 IF X<32 THEN 90
50 .
.
.
90 ? "This line sometimes follows 45."

In this example, if the value of the variable X is less than 32 in line 45, then a branch in the flow of the program is taken, and line 90 is executed next. If X is equal to or greater than 32, then the branch is not taken, and line 50 is executed next. Thus, the program flow depends on certain conditions established within the program, and for this reason, this type of transfer is called conditional transfer of control. In this example, the condition is the value of the variable X.

The BCC instruction means that if the Carry bit is clear (equal to zero), then program control must branch to a specific location. As in BASIC, if the condition is not met – in this example, if the carry bit is equal to 1 – the line next executed is not the line specified in the instruction, but rather the next line in the program.

In virtually all cases, branches in assembly language are specified by labels. A label can be almost any name you want to give to a specific line in an assembly language program. Let's look at a short example:

BCC SKIP
LDA \$0345
.
. ; other lines
. ; of the program
SKIP LDA \$4582

We'll take this one line at a time. First, we see the instruction BCC SKIP The Carry bit can either be a one or a zero at the time this instruction is executed. Let's first assume that the Carry bit is set to 1. When this line is executed, the BCC test fails; that is, since the Carry is not clear, the branch to SKIP is not taken. The next line executed loads the accumulator from address \$0345. The program then proceeds with the next line and then the next, and so on.

Now let's assume that when the BCC is executed, the Carry bit is zero. In this case, the branch is taken, since the Carry is clear, and the next line executed loads the accumulator from memory location \$4582. Then the line immediately following the SKIP line will be executed.

It should be obvious by now that in addition to the actual lines of instructions in an assembly language program, the values of each of the flags in the processor status register are an important factor in understanding a program. Instructions provided in the instruction set allow us to control these bits directly.

Still another similarity between the BCC instruction and a conditional branch in BASIC is that the branch can either be forward or backward in the program. The example above is a forward branch. To see what a backward branch looks like, let's look at the following example:

SKIP LDA \$0254
.
.
BCC SKIP

In this case, if the Carry bit is equal to zero, we branch backward from the BCC to SKIP. If it is equal to 1, the line following the BCC will be executed next.

There is an important limitation to such branches in assembly language. The BCC instruction can transfer control no further than 127 bytes forward or backward in the program. Only 1 byte is used to hold the value of the branch and any 1-byte number greater than 127 is recognized as a negative number, so if we try to branch ahead 130 bytes, the 6502 recognizes this as a negative branch of 255 - 130 = 125 bytes. Instead of jumping ahead in our program, we'd be back some considerable distance over ground we'd already traveled. Most assemblers will detect the error if we try to branch too far, and report it as such at the time of assembly, but this may be very time-consuming. It's a lot easier to try to avoid this problem while writing our programs.

One caution about relative branches: most assemblers will allow a branch of the form

BCC +7

which tells the program counter to branch forward 7 bytes if the Carry is clear when this line is executed.

CAUTION: THIS IS VERY BAD PROGRAMMING PRACTICE!!!

The problem comes when you try to read your program, or, heaven forbid, try to change it. If you insert a line shortly after this, the branch taken by this BCC will probably be wrong. The use of labels for branch target points makes your program much easier for you to read and lessens the chance of errors. Don't, under penalty of long, long, long hours of debugging, write branches like the above!

EFFECTS ON THE PROCESSOR STATUS REGISTER

None.

The only addressing mode for the BCC instruction is the Relative mode, and we have already seen how it works. Branches are either taken or not, depending on the value of the Carry bit. Branches are either forward or backward relative to the current position of the program counter, which normally points to the start of the line immediately following the BCC instruction. The BCC instruction requires 2 bytes and takes 2 machine cycles to execute.

BCS Branch on Carry Set

THE INSTRUCTION

BCS is the exact opposite of the BCC instruction. The branch is taken when the Carry bit is equal to 1 and is not taken when the Carry bit is equal to zero. In all other respects, BCS and BCC are identical. Refer to the BCC instruction for further details.

EFFECTS ON THE PROCESSOR STATUS REGISTER

None.

The only addressing mode available for the BCS instruction is the Relative mode. Its use was described above for the BCC instruction. The BCS instruction uses 2 bytes and takes 2 machine cycles to execute.

BEQ Branch on Equal to Zero

THE INSTRUCTION

The BEQ instruction is similar to the BCC and BCS instructions, but differs in one important way. Instead of using the Carry bit, the BEQ instruction uses the Zero bit as the determining factor in evaluating whether or not to take a branch. If the Zero bit is equal to 1, the branch is taken. Remember, the Zero bit will be equal to 1 only if some operation resulted in an answer of zero; thus the name Branch on Equal to Zero. If the Zero bit is equal to zero, the previous result was not equal to zero, and the branch would not be taken. This may be a little confusing at first. The best way to remember it is to understand that the Zero bit is a flag, and the flag is set when a certain condition is met. In the case of the Zero flag, the condition is a result of zero, which sets the Zero flag. Remember, we're testing for the flag being set, not for the flag being equal to zero.

LDA #0
BEQ SKIP
.
.
SKIP LDA \$2F

In this example, when we load the accumulator with zero, the Zero bit is set in the processor status register. Therefore, the line executed after the BCC is SKIP, not the next line in the program. If instead we load the accumulator with 1, the branch will not be taken, and the program flow will be in order.

EFFECTS ON THE PROCESSOR STATUS REGISTER

None.

The only available mode for the BEQ instruction is the Relative mode, discussed in detail in the section on the BCC instruction. The BEQ instruction needs 2 bytes of storage and requires 2 machine cycles to execute.

BIT Test Bits in Memory with Accumulator

THE INSTRUCTION

The BIT instruction performs an AND between the number stored in the accumulator and the number stored in another memory location addressed in the instruction, but it is different from the usual AND instruction in one very important way. The AND instruction performs the AND operation between the number in the accumulator and a number in a memory location and stores the result in the accumulator. The BIT instruction performs the AND, but does not store the result in the accumulator. "So what good is it?" you may ask.

Remember that the AND instruction does two things. First, it performs the AND and stores the result in the accumulator. Second, it sets and resets various flags in the processor status register. The BIT instruction performs the first function without storing the number, but it also performs the second, discussed below.

EFFECTS ON THE PROCESSOR STATUS REGISTER

Three flags in the processor status register are conditioned by the BIT instruction. The Negative flag is set to the value of bit 7, the most significant bit, of the byte stored in the memory location being tested, and the V (oVerflow) flag is set equal to the value of bit 6 of the same byte. The Zero flag is set if the result of the AND operation is equal to zero; it is reset if the result is not equal to zero. Some examples of the BIT instruction are given below, along with their effects on the processor status register flags. For the purpose of these examples, let's assume that memory location \$0345 contains the value #\$F3.

 A N V Z Instruction = > A N V Z #128 1 0 0 BIT \$0345 = > #128 1 1 0 #5 0 0 0 BIT \$0345 = > #5 1 1 0 #4 0 0 0 BIT \$0345 = > #4 1 1 1 #3 0 0 1 BIT \$0345 = > #3 1 1 0

This instruction is used primarily when you want to learn something about a value stored somewhere in memory without disturbing the value stored in the accumulator. For instance, you can easily learn whether the number in memory is negative, because after the BIT operation, the N flag will be set if the number was negative. Similarly, you can learn whether bit 6 of the number is a one or a zero by looking at the V flag after the BIT operation. Finally, you can determine whether an AND between the accumulator and the number in memory results in a zero value by testing the Z flag. Note that an AND operation between any number and zero will produce a zero result; so any time the number addressed in memory equals zero, the result of the BIT operation will be equal to zero and the Z flag will be set. This is quite a lot of information for an instruction which at first glance appeared to do nothing!

Only two addressing modes are available for the BIT instruction, Absolute and Zero Page.

 Mode Instruction Cycles Bytes Meaning Absolute BIT \$3420 4 3 A & contents of memory \$3420 Zero Page BIT \$F6 3 2 A & contents of memory \$F6

Since the BIT instruction simply compares the values stored in the accumulator and in a specific memory location, these two modes are sufficient for any use of BIT you may require. Between them they address the entire memory space of the computer.

BMI Branch on Minus

THE INSTRUCTION

BMI is another of the conditional branch instructions in the 6502 instruction set. It utilizes the Negative flag in the processor status register; the branch is taken if the Negative flag is set and is not taken if this flag is equal to zero. In all other respects, BMI is similar to the BCC instruction already discussed. Please read that discussion for details of conditional branch instructions, and read the discussion below of the BPL instruction for a caution concerning these two instructions.

EFFECTS ON THE PROCESSOR STATUS REGISTER

None.

The only addressing mode for the BMI instruction is the Relative mode, discussed for the BCC instruction. The BMI instruction requires 2 bytes of memory and takes 2 machine cycles to execute.

BNE Branch on Not Equal to Zero

THE INSTRUCTION

BNE is the exact opposite of the BEQ instruction. With the BNE instruction, the branch is taken if the Zero flag is equal to zero; that is, when the previous result was not equal to zero. The branch is not taken when the Zero flag is equal to 1. Refer to the discussion of the BCC instruction for details.

EFFECTS ON THE PROCESSOR STATUS REGISTER

None.

Only the Relative addressing mode, discussed under the BCC instruction, is available for the BNE instruction. The BNE instruction requires 2 bytes of memory and takes 2 machine cycles to execute.

BPL Branch on Plus

THE INSTRUCTION

This instruction is the exact opposite of BMI. The branch is taken following the BPL instruction if the Negative flag is equal to zero and is not taken if this flag is equal to 1. One caution should be mentioned for this pair of instructions: in order for the branch to be correctly determined, the Negative flag must, of course, have been correctly conditioned prior to executing either the BMI or BPL instruction. Since not all other instructions condition the Negative flag, be sure that you use one which does correctly condition this flag before utilizing either the BMI or BPL instruction.

EFFECTS ON THE PROCESSOR STATUS REGISTER

None.

Only the Relative addressing mode is available for the BPL instruction. Please see the discussion of the BCC instruction for details. The BPL instruction requires 2 bytes of memory and takes 2 machine cycles to execute.

BRK Break

THE INSTRUCTION

The BRK instruction is somewhat analogous to the BASIC STOP command. We know that the STOP command causes the program being executed to stop; at that point control is returned to the BASIC cartridge, which signals that it is back in command by telling you what happened and printing READY to the screen.

The primary use of the BRK instruction is in debugging your program after it has been written, but before it's working quite the way you intended. In BASIC, we frequently go through this debugging process by inserting STOP instructions at various places in the program and then running the program to see if we get to the various STOPS. In assembly language programming, BRKs can be used in exactly the same way. You can insert a number of BRK instructions throughout your program and then try to run it. If you don't reach the BRK instructions, you know that your program is "hanging up" somewhere prior to that instruction. Most available debuggers will print out the values of the 6502 registers whenever a BRK instruction is encountered in a program; this makes the job of debugging somewhat easier. Even with such aids, debugging a long assembly language program should not be attempted by the faint of heart, at least not unless there is a big slice of time available with nothing else to do.

EFFECTS ON THE PROCESSOR STATUS REGISTER

None.

Only one addressing mode is available for the BRK instruction, the Implied mode. This is a single-byte mode, and for the BRK instruction it requires 7 machine cycles to execute.

BVC Branch on Overflow Clear

THE INSTRUCTION

BVC is another of the conditional branch instructions in the 6502 instruction set; it utilizes the Overflow flag of the processor status register. If the V flag is set, the branch is not taken, but if the V flag is clear (equal to zero), the branch is taken. See the discussion of the BCC instruction for further details on conditional branch instructions.

EFFECTS ON THE PROCESSOR STATUS REGISTER

None.

The BVC instruction utilizes only the one addressing mode common to all of the conditional branch instruction, the Relative mode. The instruction requires 2 bytes and takes 2 machine cycles to execute.

BVS Branch on Overflow Set

THE INSTRUCTION

The BVS instruction is the exact opposite of the BVC instruction. If the Overflow flag in the processor status register is set (equal to 1), the branch is taken, and if the V flag is clear (equal to zero), the branch is not taken. You can find the details of relative branching in the discussion of the BCC instruction.

EFFECTS ON THE PROCESSOR STATUS REGISTER

None.

The BVS instruction utilizes only the Relative mode of addressing.

CLC Clear the Carry Bit

THE INSTRUCTION

The CLC instruction has a direct and constant effect on a flag in the processor status register. It clears the Carry bit – that is, sets it equal to zero, whether it was initially zero or 1. It's most commonly used prior to addition with the ADC instruction. Since the ADC instruction always adds the Carry bit into the sum, we generally need to be sure that this bit is equal to zero before addition. This is the only way to be sure that 2 plus 1 will equal 3, and not 4 at times. Almost universally, the typical set of instructions to add two numbers will be:

LDA #2
CLC

We load the accumulator with the first number – in this case, 2. Then we clear the Carry bit, because we have no way of knowing for certain the value of this bit at any time without a lot more code. By setting the Carry bit to zero, we know we'll get an accurate sum. We complete the operation by adding with carry the number 1. Remember that the sum, 3 in this case, will be stored in the accumulator at the completion of the addition; other lines will probably do something with this sum, such as store it in memory or utilize it in some further operation.

EFFECTS ON THE PROCESSOR STATUS REGISTER

The only effect CLC has on the processor status register is to always set the Carry bit to zero.

The sole addressing mode available for the CLC instruction is the Implied mode. The instruction is only 1 byte long and requires only 2 machine cycles to execute.

CLD Clear the Decimal Flag

THE INSTRUCTION

As we have already discussed, the 6502 can operate in either the decimal mode or the binary mode. The CLD instruction clears the decimal flag in the processor status register and resets the 6502 to operate in binary rather than decimal mode. In this book, we'll use the binary mode for most examples, but we'll briefly cover the decimal mode here. In this mode, each nibble of a byte represents a single decimal digit. The coding scheme is referred to as Binary Coded Decimal (BCD) and is given below:

Bits      Represent
0000            0
0001            1
0010            2
0011            3
0100            4
0101            5
0110            6
0111            7
1000            8
1001            9

The difference between binary and decimal coding shows up when addition or subtraction takes place. For example, let's try the following code:

LDA \$0345 ; Contains #\$59
CLC       ; Put before an add instruction

What number is contained in the accumulator after execution of these lines? We would normally think that this number should be #\$6C, and if the addition were done in the binary mode we'd be correct. But suppose that we had first put the 6502 into the decimal mode. In that case, the number stored in the accumulator would be 72 (\$48), because the 6502 would interpret the bytes at locations \$0345 and \$0302 as binary-coded decimal numbers, and would add them in decimal mode: 59 + 13 = 72.

As was mentioned before, the examples in this book are all in binary form. The decimal mode may be used, however, when a result needs to be displayed to the screen quickly. Since each nibble of the number represents a decimal digit, by masking the appropriate digit using the AND instruction and then sending it to the screen, we can display a number quickly, without the need to interconvert between binary and decimal nomenclature.

EFFECTS ON THE PROCESSOR STATUS REGISTER

The CLD instruction directly sets the Decimal flag of the processor status register to zero, thus clearing it. No other effects occur.

As with all instructions operating directly on flags in the processor status register, the only addressing mode available for the CLD instruction is the Implied mode. The instruction requires only 1 byte of memory and takes 2 machine cycles to execute.

CLI Clear the Interrupt Flag

THE INSTRUCTION

The CLI instruction operates directly on the processor status register to clear the Interrupt flag; that is, to set the flag equal to zero. This presumably follows some instruction which had set this flag. Remember that when the Interrupt flag is set, maskable interrupts are disabled. This is important for ATARI programming because several different types of interrupts are used routinely in many programs, and if the I flag is set, they cannot occur. The vertical blank interrupt and the display list interrupt are included in this category. The CLI instruction allows these interrupts to occur.

EFFECTS ON THE PROCESSOR STATUS REGISTER

The CLI instruction operates directly to clear the I flag and has no effect on any of the other flags in the processor status register.

The CLI instruction utilizes only one addressing mode, the Implied mode, and takes 1 byte of memory and 2 machine cycles to execute.

CLV Clear the Overflow Flag

THE INSTRUCTION

CLV is just like the two previous instructions, CLD and CLI, which clear a flag in the processor status register. In the case of the CLV instruction, the Overflow flag is cleared.

EFFECTS ON THE PROCESSOR STATUS REGISTER

The CLV instruction clears the Overflow flag, but has no effect on any of the other flags in the processor status register.

Like the other instructions operating directly on the processor status register, CLV has only one mode of address, the Implied mode.

CMP Compare Memory and the Accumulator

THE INSTRUCTION

In BASIC, we can compare two values and determine whether they are equal, whether A is greater than B; or whether A is less than B. Generally, this is done in an IF statement of this type:

35 IF A<B THEN ...

Using the 6502 instruction set, we can also compare two numbers, although in a slightly different way. One of the numbers to be compared must be in the accumulator, and the other may be anywhere in the memory of the computer. The instruction CMP subtracts the contents of the specified memory location from the value stored in the accumulator and sets the various processor status register flags appropriately after this subtraction. Note that the value stored in the accumulator does not change following the CMP instruction. The subtraction only sets the flags; it does not change the value originally stored in the accumulator. Knowing the values of the flags in the processor status register, we can deduce the results of the comparison. Let's first discuss the changes in the processor status register, and then we'll work on some CMP examples.

EFFECTS ON THE PROCESSOR STATUS REGISTER

The CMP instruction sets the Zero flag if the number in memory and the number stored in the accumulator are equal. If they are not equal, the Zero flag is reset to zero. The Negative flag is set following the CMP instruction if the result of the subtraction is greater than 127 (that is, the number has its most significant bit equal to one). Otherwise, the Negative flag is reset to zero. The Carry flag is set when the value stored in memory is less than or equal to the number stored in the accumulator. C is reset when the number stored in memory is less than that stored in the accumulator. Let's look at a few examples of the CMP instruction, assuming that memory location \$0345 contains #26:

 A Z N C Instruction = > A Z N C Comment #26 0 0 0 CMP \$0345 = > #26 1 0 1 Z, C set by A = \$0345 #48 0 0 0 CMP \$0345 = > #48 0 0 1 Z reset, C set by A > \$0345 #130 0 1 0 CMP \$0345 = > #130 0 0 1 N reset by A - \$0345 < 128 #8 0 0 0 CMP \$0345 = > #8 0 1 0 N set by A - \$0345 > 127

In the first example, the two numbers being compared were equal, causing the subtraction to produce a result of zero. This result set the Zero flag. Since the number in memory was equal to the number in the accumulator, the Carry flag was also set.

In the second example, the Zero flag was not set, since the result did not equal zero; the Negative flag was not set, since the result was positive (+22); and the Carry bit was set, since the number in memory was less than the number in the accumulator.

In the third example, the number began as a negative, with the Negative flag set. Since the result was not equal to zero, the Zero bit was reset. The result of the subtraction, 130 minus 26, was the positive number 104, so the Negative flag was reset. Finally, since the value stored in \$0345 was less than the value of #130 stored in the accumulator, the Carry bit was set.

This third example demonstrates an important point about the CMP instruction. A negative number is clearly less than a positive number, but the result of this comparison made it appear as if the negative number was larger. The CMP instruction does not use signed arithmetic; it simply compares two numbers between zero and 255, treating both numbers as positive integers. If you use signed arithmetic, you'll need to correct for this when comparing two numbers.

In the fourth example, the Zero bit was not set, since the result was not equal to zero. The Negative bit was set, since #8 - #26 = #238, which is a negative number. Finally, since the number in the accumulator was smaller than the number in memory, the Carry bit was reset with zero.

We can also look at these effects to determine how to test for the various results. The table below describes several values of the accumulator and memory, along with branch instructions which will be taken following a CMP instruction. The code looks like this:

LDA #...
CMP \$....
B.. destination

Now we'll see which branches will be taken using various values for the two numbers.

A  Mem.  BCS, BPL, BNE
8      8      BEQ, BCS, BPL
9      8      BCS, BPL, BNE
8      9      BMI,  BCC, BNE

Now we can see how to structure some code which will compare two numbers and take appropriate action, depending on the results obtained. Let's suppose that we want to duplicate the following BASIC code in assembly language:

25 IF R<B THEN GOTO Q

In ATARI BASIC, this means that the branch to line Q will be taken if the value of the variable R is less than the value of the variable B at the time line 25 is executed. In assembly language, the same code looks like this:

LDA R ;load A from memory location R
CMP B ;compare to memory location B
BCC Q ;take branch if Carry reset

CMP uses the same eight addressing modes discussed in Chapter 5 for the LDA instruction.

 Mode Instruction Cycles Bytes Meaning Immediate CMP #2 2 2 A - #2 Absolute CMP \$3420 4 3 A - contents of memory \$3420 Zero Page CMP \$F6 3 2 A - contents of memory \$F6 Zero Page,X CMP \$F6,X 4 2 A - contents of memory \$F6 + X Absolute,X CMP \$3420,X 4 3 A - contents of memory \$3420 + X Absolute,Y CMP \$3420,Y 4 3 A - contents of memory \$3420 + Y Indexed Indirect CMP (\$F6,X) 6 2 A - contents of address at \$F6 + X Indirect Indexed CMP (\$F6),Y 5 2 A - contents of (address at \$F6) + offset Y

CPX Compare Index Register X with Memory

THE INSTRUCTION

This instruction compares the values in the X register and a specific memory location, in contrast to the CMP instruction, which compares the values in the accumulator and a memory location. In all other respects, the CPX and CMP instructions are identical. CPX is used primarily to test the value in register X, especially when it is being used as an index, in order to determine if it has reached the final desired value. For example, when the X register is being used as a loop counter and you wish to determine when to branch out of the loop, the CPX instruction, followed by an appropriate branch instruction, will give you the answer.

EFFECTS ON THE PROCESSOR STATUS REGISTER

If the two numbers being compared are equal, the Zero flag will be set (made equal to 1); otherwise, it will be reset (made equal to zero). If the result of the subtraction is greater than 127, the Negative flag will be set; otherwise, it will be reset. Finally, if the number in memory is less than or equal to the number stored in the X register, the Carry flag will be set; otherwise, it will be reset. Please refer to the CMP instruction for more details.

The CPX instruction utilizes the three addressing modes outlined below.

 Mode Instruction Cycles Bytes Meaning Immediate CPX #2 2 2 X - #2 Absolute CPX \$3420 4 3 X - contents of memory \$3420 Zero Page CPX \$F6 3 2 X - contents of memory \$F6

CPY Compare Index Register Y with Memory

THE INSTRUCTION

CPY is identical to CPX or CMP in all respects, except that it uses the Y instead of the X register or the accumulator. As with the CPX instruction for the X register, when you need to determine whether the index register Y has reached a certain value, use the CPY instruction. Refer to the CMP and CPX sections of this Appendix for details.

EFFECTS ON THE PROCESSOR STATUS REGISTER

Please refer to the CMP instruction for a detailed description of the effects of CPY on the processor status register.

The CPX and CPY instructions are identical in their addressing modes, examples of which are shown below:

 Mode Instruction Cycles Bytes Meaning Immediate CPY #2 2 2 Y - #2 Absolute CPY \$3420 4 3 Y - contents of memory \$3420 Zero Page CPY \$F6 3 2 Y - contents of memory \$F6

DEC Decrement Memory

THE INSTRUCTION

In order to decrement (decrease by 1) any memory location, the DEC instruction may be used. There are actually two ways to decrement a memory location. The first, and by far the easiest, is to use DEC directly. The second, and by far the more cumbersome, is to load the accumulator from that memory location, subtract 1, and then store the resulting number back into the original memory location. You can see why a DEC instruction was included in the 6502 instruction set.

EFFECTS ON THE PROCESSOR STATUS REGISTER

If the decrementing process results in a number equal to zero in the memory location addressed, the Zero flag in the processor status register will be set. If the result is any number but zero, the Zero flag will be reset. If the number resulting from the DEC instruction is negative (greater than 127), the Negative flag will be set; otherwise, it will be reset. It is therefore possible to determine when a decrementing instruction has produced either a zero or negative result without ever loading the number in question into the accumulator: simply check the status of either the Z or the N flag in the processor status register.

Four addressing modes are available for the DEC instruction, as listed below:

 Mode Instruction Cycles Bytes Meaning Absolute DEC \$3420 6 3 DEC Contents of memory \$3420 Zero Page DEC \$F6 5 2 DEC Contents of memory \$F6 Zero Page,X DEC \$F6,X 6 2 DEC Contents of memory \$F6 + X Absolute,X DEC \$3420,X 7 3 DEC Contents of memory \$3420 + X

DEX Decrement the X Register

THE INSTRUCTION

DEX specifically decrements the X register and is used primarily when the X register is being used as the index of a loop. Each time through the loop you decrement the register once. When the Z flag is set following this decrementing, you can branch out of the loop, knowing it has completed the predetermined number of cycles.

EFFECTS ON THE PROCESSOR STATUS REGISTER

Like the DEC instruction, the DEX instruction will set or reset both the Negative flag and the Zero flag in the processor status register. By testing these flags, a programmer can determine the state of the X register.

Only one addressing mode is available for the DEX instruction, and as you might expect, it is the Implied mode, since the addressing can be inferred by the nature of the instruction. The instruction requires only 1 byte and takes 2 machine cycles to execute.

DEY Decrement the Y Register

THE INSTRUCTION

DEY is the Y register counterpart to the DEX instruction. It decrements the Y register by 1.

EFFECTS ON THE PROCESSOR STATUS REGISTER

The effects of the DEY instruction are the same as those of the DEC and DEX instructions already discussed.

Like the DEX instruction, the DEY instruction uses only the Implied mode, requires 1 byte of memory, and takes 2 machine cycles to execute.

EOR Exclusive OR

THE INSTRUCTION

The EOR instruction is most like the AND instruction. Remember that AND performs a bit-by-bit AND: if a bit is set in both of the numbers being compared, the bit will be set in the resulting answer. The EOR instruction performs a bit-by-bit EOR. If a bit is set in one, and only one, of the numbers addressed, it is set in the answer. If the bit is set in both or neither, there is a zero in that position of the answer. The resulting number is stored in the accumulator. An example of this is shown below:

LDA #133
EOR #185

Again, the simplest way to determine the correct answer for the EOR operation is to visualize the numbers in their binary form:

Dec.      Binary
#133 =  #%10000101
#186 =  #%10111010
Result =  #%00111111  =  #63

Bit 7, which was set in both numbers, is equal to zero in the answer. Similarly, bit 6, which is equal to zero in both numbers, is also equal to zero in the answer. Only those bits which were set in only one of the numbers are set in the answer – bits 0 through 5.

The most common use of the EOR instruction is in complementing a number. To do this, we EOR the number with #\$FF, a number in which each bit is set. For instance, to complement the number 143, we EOR it with #\$FF:

#143  = #%10001111
#\$FF = #%11111111
Result  = #%01110000  =  #112

EFFECTS ON THE PROCESSOR STATUS REGISTER

If the resulting number, residing in the accumulator, is negative (greater than 127), the Negative flag is set; otherwise, it is reset. If the result of the EOR instruction is equal to zero, the Zero flag is set; otherwise, it is reset.

The EOR instruction utilizes the same 8 addressing modes as does the LDA instruction; these are detailed in Chapter 5. Brief examples are given below:

 Mode Instruction Cycles Bytes Meaning Immediate EOR #2 2 2 A EOR #2 Absolute EOR \$3420 4 3 A EOR memory \$3420 Zero Page EOR \$F6 3 2 A EOR memory \$F6 Zero Page,X EOR \$F6,X 4 2 A EOR memory \$F6 + X Absolute,X EOR \$3420,X 4 3 A EOR memory \$3420 + X Absolute,Y EOR \$3420,Y 4 3 A EOR memory \$3420 + Y Indexed Indirect EOR (\$F6,X) 6 2 A EOR address at \$F6 + X Indirect Indexed EOR (\$F6),Y 5 2 A EOR (address at \$F6) + offset Y

INC Increment Memory

THE INSTRUCTION

The INC instruction is the exact opposite of the DEC instruction, causing the value stored in any addressed memory location to be increased by 1.

EFFECTS ON THE PROCESSOR STATUS REGISTER

The INC instruction sets the Negative flag if the resulting number is greater than 127; otherwise, it resets the Negative flag. It also sets the Zero flag if the resulting number is equal to zero; otherwise, it resets the Zero flag.

INC utilizes the same four addressing modes utilized by the DEC instruction. Consult the examples below:

 Mode Instruction Cycles Bytes Meaning Absolute INC \$3420 6 3 INC contents of memory \$3420 Zero Page INC \$F6 5 2 INC contents of memory \$F6 Zero Page,X INC \$F6,X 6 2 INC contents of memory \$F6 + X Absolute,X INC \$3420,X 7 3 INC contents of memory \$3420 + X

INX Increment the X Register

THE INSTRUCTION

The INX instruction is the exact opposite of the DEX instruction. It increments the value stored in the X register by 1 and is used to increase the value of the index register in loops, as shown in Chapters 7 to 10.

EFFECTS ON THE PROCESSOR STATUS REGISTER

If the increment causes the X register to be equal to zero, the Zero flag is set; otherwise, it is reset. If the resulting number is negative, the Negative flag is set; otherwise, it is reset.

As with the other instructions of this type, the only addressing mode available is the Implied mode, requiring 1 byte of memory and 2 machine cycles to execute.

INY Increment the Y Register

THE INSTRUCTION

Similar to the INX instruction just discussed, and the exact opposite of the DEY instruction, INY causes the Y register to be increased by 1.

EFFECTS ON THE PROCESSOR STATUS REGISTER

If the results of the increment cause the number stored in the Y register to be negative, the Negative flag is set; otherwise, it is reset. If the Y register equals zero following the increment, the Zero flag is set; otherwise, it is reset.

The only addressing mode available for the INY instruction is the Implied mode, taking 1 byte of memory and 2 machine cycles to execute.

THE INSTRUCTION

We have discussed several examples of conditional transfer of control using branching instructions. These are the counterparts of the BASIC IF statement. However, we know that BASIC also has an unconditional transfer of control instruction, the GOTO statement:

30 GOTO Q
40 .

We know that the line executed after line 30 will be line Q, not line 40. This does not depend on anything within the program; that is, it is totally unconditional. Every time line 30 is executed, line Q will be the next line executed.

Assembly language has its counterpart of the GOTO statement – the JMP instruction. This is its form:

JMP Q

It works exactly like the BASIC example above. Every time the JMP is executed, line Q will be the next line executed, regardless of any conditions established while running the program. This is a totally unconditional transfer of control.

EFFECTS ON THE PROCESSOR STATUS REGISTER

None.

The JMP instruction has only two addressing modes. The first is the Absolute mode, in which the jump takes place to a specific memory location, as described in the example above. This mode uses 3 bytes of memory and requires 3 machine cycles to execute.

The second addressing mode is the Indirect mode, which is used only for the JMP instruction. To use this mode, we must first set up an indirect memory location somewhere in memory. Let's suppose that we would like to JMP indirectly to memory location \$0620. We must first decide where in memory we will store the indirect address; here we'll use locations \$0423 and \$0424. We first store the byte #\$20 in memory location \$0423 and the byte #\$06 in memory location \$0424. Remember, for the 6502, the low byte comes first, followed by the high byte of the address. The indirect jump is then of this form:

JMP (\$0423)

The parentheses indicate that it is an indirect jump; and the low address of the indirect address is given in the instruction. It is also possible to set an address label for \$0423, in which case the instruction could be written like this:

JMP (Q)

Figure A-1 illustrates the indirect jump graphically. The indirect JMP instruction requires 3 bytes and takes 5 machine cycles to execute.

Location Contents
0421
A9

0422
B3

0423
 20 06
=\$0620
0424
0425
95

0426
DE

Fig A-1 Indirect jump JMP (\$0423)

THE INSTRUCTION

In BASIC, we can use subroutines to perform repetitive tasks, and we can do the same thing in assembly language. The BASIC command GOSUB has an exact counterpart in assembly language – JSR. This instruction pushes the value of the program counter onto the stack, where it remains until the subroutine is completed. The value is then pulled off the stack so that the program may continue execution in the appropriate place. In the program below, first the LDA is executed, then the subroutine at Q, and then the STA.

LDA #124
JSR Q
STA \$4657

One note about the use of subroutines in assembly language is appropriate here. In BASIC, programs run more rapidly if frequently used subroutines are all located as close to the beginning of the program as possible. Because the BASIC interpreter starts scanning the program for the target line from the beginning, this practice avoids the need to search the whole program to find the subroutine. In assembly language, this is not the case. At the time of assembly, the actual address of the subroutine is placed following the code for the JSR instruction, so the subroutine can be located anywhere. In practice, it's a good idea to group all your subroutines together, usually at the end of your assembly language program, both for readability and for ease of access for changes, but it's up to you. The program will execute in exactly the same way no matter where you locate the subroutines.

EFFECTS ON THE PROCESSOR STATUS REGISTER

None.

The JSR instruction utilizes only the Absolute addressing mode. It uses 3 bytes of memory and 6 machine cycles to execute.

THE INSTRUCTION

The LDA instruction loads the accumulator with a number, either directly or by copying some value stored in one of the memory locations of the computer. Along with the STA instruction, it is probably the most frequently used instruction of the entire 6502 set. Its main uses are for placing specific values into memory; for example,

LDA #2
STA \$0344

and for transferring the contents of one memory location to another; for example,

LDA \$0620
STA \$0344

This instruction was thoroughly described in Chapter 4.

EFFECTS ON THE PROCESSOR STATUS REGISTER

If the number loaded into the accumulator is greater than 127, the Negative flag is set; otherwise, it is reset. If the number loaded into the accumulator is equal to zero, the Zero flag is set; otherwise, it is reset.

The eight addressing modes availabe for the LDA instruction were thoroughly described in Chapter 5. The eight modes are briefly listed below:

 Mode Instruction Cycles Bytes Meaning Immediate LDA #2 2 2 #2 ⇒ A Absolute LDA \$3420 4 3 contents of memory \$3420 ⇒ A Zero Page LDA \$F6 3 2 contents of memory \$F6 ⇒ A Zero Page,X LDA \$F6,X 4 2 contents of memory \$F6 + X ⇒ A Absolute,X LDA \$3420,X 4 3 contents of memory \$3420 + X ⇒ A Absolute,Y LDA \$3420,Y 4 3 contents of memory \$3420 + Y ⇒ A Indexed Indirect LDA (\$F6,X) 6 2 contents of address at \$F6 + X ⇒ A Indirect Indexed LDA (\$F6),Y 5 2 contents of (address at \$F6) + offset Y ⇒ A

THE INSTRUCTION

The LDX instruction directly loads the X register, and is exactly analogous to the LDA instruction for the accumulator. It allows direct loading of the index register and is frequently used in assembly language programs.

EFFECTS ON THE PROCESSOR STATUS REGISTER

If the number loaded into the X register is greater than 127, the Negative flag is set; otherwise, it is reset. If the number loaded into the X register is equal to zero, the Zero flag is set; otherwise, it is reset.

LDX utilizes five addressing modes. A summary is given below:

 Mode Instruction Cycles Bytes Meaning Immediate LDX #2 2 2 LDX #2 Absolute LDX \$3420 4 3 LDX contents of memory \$3420 Zero Page LDX \$F6 3 2 LDX contents of memory \$F6 Zero Page,Y LDX \$F6,Y 4 2 LDX contents of memory \$F6 + Y Absolute,Y LDX \$3420,Y 4 3 LDX contents of memory \$3420 + Y

THE INSTRUCTION

The LDY instruction, like the LDA and LDX instructions, allows direct loading of the 6502. In this case, the load is into the Y register, but in all other respects LDY is identical to both the LDX and LDA instructions.

EFFECTS ON THE PROCESSOR STATUS REGISTER

As with the LDX instruction, if the number loaded into the Y register by LDY is greater than 127, the Negative flag is set; otherwise, it is reset. If the number loaded is equal to zero, the Zero flag is set; otherwise, it is reset.

Five addressing modes are available for the LDY instruction, as outlined here:

 Mode Instruction Cycles Bytes Meaning Immediate LDY #2 2 2 LDY #2 Absolute LDY \$3420 4 3 LDY contents of memory \$3420 Zero Page LDY \$F6 3 2 LDY contents of memory \$F6 Zero Page,X LDY \$F6,X 4 2 LDY contents of memory \$F6 + X Absolute,X LDY \$3420,X 4 3 LDY contents of memory \$3420 + X

LSR Logical Shift Right

THE INSTRUCTION

This instruction is the exact opposite of ASL. The LSR instruction forces the most significant bit (bit 7) of a number to zero and rotates each bit down 1 position, with the least significant bit (bit 0) ending up in the Carry bit.

76543210 Carry
before: 0   ⇒   10110101  ⇒   0
after:                 01011010         1

We can see the shift in the bits within the number and the transfer of the zero into the high bit, as well as the transfer of the low bit into the Carry.

Remember that an ASL instruction causes a number to double its value. Since each bit in a binary number is exactly one-half the value of its left-hand neighbor, the LSR instruction divides a number by 2, and the Carry bit represents the remainder of the division. In the example above, these are the 2 bytes before and after the LSR:

#%10110101   =   #181
#%01011010   =   #90 with C =1

We can see that the division worked as we expected.

CAUTION:    If we are using signed arithmetic, then the first byte in the example is not 181, but rather -(255 - 181) = -74, and we all know that 90 is not half of -74. To divide a negative number by 2, we have to remember that it is negative, then convert it to its positive counterpart, divide it by 2, and then convert it back to a negative number. Whew! Let's see how to do this:

LDA #\$FE ; -2
EOR #\$FF ; Complement it
ADC #1   ; Now it's +2
LSR A    ; Divide by two
EOR #\$FF ; Complement again
STA ...  ; the answer, -1 (\$FF)

From this example, we can see that to interconvert positive and negative numbers, we need only to EOR the number with #\$FF, and add 1 to the result.

EFFECTS ON THE PROCESSOR STATUS REGISTER

Since the high bit of the number being addressed is always forced to zero, the Negative flag is always reset by this operation. If the result of the LSR instruction is equal to zero, the Zero flag is set; otherwise, it is reset. Finally, the Carry flag is set if the least significant bit of the original number was a 1, and it is reset if this bit was a zero.

Five addressing modes are available for the LSR instruction:

 Mode Instruction Cycles Bytes Meaning Absolute LSR \$3420 6 3 LSR contents of memory \$3420 Zero Page LSR \$F6 5 2 LSR contents of memory \$F6 Zero Page,X LSR \$F6,X 6 2 LSR contents of memory \$F6 + X Absolute,X LSR \$3420,X 7 3 LSR contents of memory \$3420 + X Accumulator LSR A 2 1 LSR contents of accumulator

NOP No Operation

THE INSTRUCTION

The NOP instruction acts as you might expect from its name; it does nothing! So why have it at all? The NOP instruction can be used to hold space for modifying instructions in a program, or in debugging a program, to eliminate an instruction without having to change the location in memory of all succeeding instructions.

EFFECTS ON THE PROCESSOR STATUS REGISTER

None.

As can be deduced from its operation, the only addressing mode available for the NOP instruction is the implied mode. It takes 1 byte of memory and requires 2 machine cycles to execute.

ORA OR Memory with the Accumulator

THE INSTRUCTION

The ORA instruction is the last of the three logical instructions of the 6502. The first two are the AND and EOR instructions. The ORA instruction compares two numbers bit by bit, and if a bit is set to 1 in either or both numbers, that bit will also be set to 1 in the resulting number. Let's look at an example:

Number 1:        #%10100101
Number 2:        #%01101100
ORA result:  =    #%11101101

The primary use of ORA is to set a particular bit of a number to 1. For instance, if you have a number in memory location \$4235 and you need to use it with the least significant bit (bit 0) set to 1, you simply load the accumulator with the number 1 and ORA with memory location \$4235. The accumulator will then contain the number which was in memory location \$4235, with its least significant bit set equal to 1.

EFFECTS ON THE PROCESSOR STATUS REGISTER

If the number residing in the accumulator following the ORA instruction is equal to zero, the Zero flag will be set; otherwise, it will be reset. If the resulting number is greater than 127, the Negative flag will be set; otherwise, it will be reset.

The ORA instruction utilizes the following eight addressing modes:

 Mode Instruction Cycles Bytes Meaning Immediate ORA #2 2 2 A OR #2 Absolute ORA \$3420 4 3 A OR contents of memory \$3420 Zero Page ORA \$F6 3 2 A OR contents of memory \$F6 Zero Page,X ORA \$F6,X 4 2 A OR contents of memory \$F6 + X Absolute,X ORA \$3420,X 4 3 A OR contents of memory \$3420 + X Absolute,Y ORA \$3420,Y 4 3 A OR contents of memory \$3420 + Y Indexed Indirect ORA (\$F6,X) 6 2 A OR contents of address at \$F6 + X Indirect Indexed ORA (\$F6),Y 5 2 A OR contents (address at \$F6) + offset Y

PHA Push the Accumulator onto the Stack

THE INSTRUCTION

In assembly language programming, we generally have several places in which to store a value temporarily. We can place it into some reserved memory location or place it in the X or Y registers or push it onto the stack. Of these methods, the only one which won't disturb any other stored information (as the TAY or TAX instructions might), is the PHA instruction, which will push the number onto the stack. However, great caution must be exercised when using the stack to store information. Remember that the stack is used to hold return addresses so that the JSR instruction will know where to return following the completion of the subroutine. Pushing extraneous numbers onto the stack can result in computer crashes unless you take care not to interfere with the return addresses, since the 6502 will try to return to a virtually random address; the odds of finding a valid instruction at such an address are vanishingly small.

EFFECTS ON THE PROCESSOR STATUS REGISTER

None.

The only addressing mode available for the PHA instruction is the Implied mode. The instruction requires only 1 byte of memory and 3 machine cycles to execute.

PHP Push the Processor Status Register onto the Stack

THE INSTRUCTION

The PHP instruction takes the byte containing the flags of the processor status register and pushes it onto the stack. Its purpose is to save the contents of the processor status register for some future operation while intermediate steps are being processed. The cautions for using PHP are similar to those for the PHA instruction: be sure you don't interfere with information that would normally be placed onto the stack, such as return addresses for subroutine operations.

EFFECTS ON THE PROCESSOR STATUS REGISTER

None.

As might be expected, the only addressing mode for the PHP instruction is the Implied mode. The PHP instruction is a 1-byte instruction and requires 3 machine cycles to execute.

PLA Pull the Accumulator from the Stack

THE INSTRUCTION

This instruction is the counterpart to the PHA instruction. Obviously, if we have a way to push the value stored in the accumulator onto the stack, we should also have a way to get it back again. The PLA instruction removes the top value from the stack and places it into the accumulator for further use.

We will discuss one important use of PLA, but first we need to know a little about machine language subroutines that are to be used in BASIC. Let's suppose that since ATARI BASIC has no true AND function, we want to write a machine language subroutine that will AND two numbers together and return the answer to BASIC. The first problem we face is how to get the two numbers to our machine language routine. There are two ways to do this.

The first method is universal and can be used on most microcomputers. First, we calculate the high and low bytes of the two numbers and then POKE each of these bytes into memory. The machine language subroutine then accesses these memory locations to obtain the numbers, and, after ANDing them together, places the answer in memory, where it can be accessed by your BASIC program. The BASIC program looks like this:

10 HIGHP=INT(P/256):REM GETS HIGH BYTE OF P
20 LOWP = P-256*HIGHP:REM GETS LOW BYTE OF P
30 HIGHQ = INT(Q/256):REM GETS HIGH BYTE OF Q
40 LOWQ=Q-256*HIGHQ:REM GETS LOW BYTE OF Q
50 POKE ADDR1,LOWP:REM PUTS LOWP INTO MEMORY
60 POKE ADDR2,HIGHP:REM PUTS HIGHP INTO MEMORY
70 POKE ADDR3,LOWQ:REM PUTS LOWQ INTO MEMORY
80 POKE ADDR4,HIGHQ:REM PUTS HIGHQ INTO MEMORY
90 X = USR(1536):REM ACCESSES MACHINE LANGUAGE SUBROUTINE

Although this method works, it's a bit clumsy. But for a number of microcomputers on the market, this is the only method available. However, your ATARI has a much more elegant and simple solution to the problem.

The solution involves passing parameters from BASIC to machine language and back again. These parameters can be numbers, addresses of strings, or virtually any type of constant or variable in your BASIC program. The method for passing parameters to a machine language program is simply to list the parameters to be passed after the address of the machine language routine in the USR call, separating the parameters by commas. Here is the program to do this:

Yes! Only one line! How do we do this?

Your ATARI takes P and Q, breaks them down into high and low bytes for you, and places them onto the stack, where they can be retrieved by your machine language program using the PLA instruction. It's also possible, by storing the answer obtained by your machine language routine into \$D4 and \$D5 (low byte first), to have the variable ANSWER automatically contain the right answer after line 10 is executed.

There is one crucial detail concerning this use of parameter passing. Since the ATARI allows parameters to be passed in a USR call, it also tells the machine language routine how many parameters are being passed. It does this even if no parameters are being passed! This information is automatically pushed onto the stack as a single byte as soon as the BASIC line is executed. In the case of line 10 above, therefore, the stack will have the number 2 pushed onto it before the high and low bytes of P and Q are placed there. This byte then fouls up the return address, so the machine language program would fail to return to the right place in the BASIC program. Your computer will crash. In all likelihood, you'll have to turn the power off and on again, losing your program. How can we prevent this?

The answer is as simple as it is obvious. Just begin every machine language subroutine you write for a BASIC program with a PLA instruction. PLA will get rid of this extra byte on the stack, and then you can proceed with the remainder of your machine language routine. This byte that PLA pulled from the stack into the accumulator can be used as a check on your BASIC program, if you desire. For instance, we already know that the number in this example should be 2. If it's not, someone made a mistake in the BASIC program. We already know that our machine language routine will fail if two parameters are not passed to it. Therefore, we could build code into our machine language routine to check the first byte pulled into the accumulator. If it is not a 2, the program could branch to some routine which notifies the user of the error by printing an error message or passing an error code back into ANSWER or using another method.

In any case, it is critical to remember that when you write machine language subroutines for use in BASIC programs, you must include the extra PLA to remove the number of parameters from the stack or your computer will crash.

EFFECTS ON THE PROCESSOR STATUS REGISTER

If the number which the PLA instruction pulls from the stack is greater than 127, the Negative flag will be set; otherwise, it will be reset. If the number pulled from the stack is equal to zero, the Zero flag will be set; otherwise, it will be reset.

The only addressing mode available for the PLA instruction is the Implied mode, requiring only 1 byte of memory and 4 machine cycles to execute.

PLP Pull the Processor Status Register from the Stack

THE INSTRUCTION

PLP reverses the PHP instruction by removing the top byte from the stack and placing it into the processor status register. PLP is used to restore things to the way they were at the time the PHP instruction was executed.

EFFECTS ON THE PROCESSOR STATUS REGISTER

The PLP instruction affects all of the flags in the processor status register, since they will all be changed to the values contained in the byte pulled from the stack.

The only addressing mode available for the PLP instruction is the Implied mode. PLP is a 1-byte instruction and requires 4 machine cycles to execute.

ROL Rotate Left

THE INSTRUCTION

ROL is similar to the ASL and LSR instructions, but with one significant difference. When those two instructions are executed, the rotation of the bits forces a zero into the high or low bit, respectively. The ROL instruction is a true rotation, in which the Carry bit is placed into bit zero of the number, each bit of the number is moved one position to the left, and the most significant bit of the number is rotated into the Carry bit. This can be shown pictorially as follows:

76543210          C
before:       10010101     ⇐   0
C   76543210
after:     1   00101010

Note that in contrast to the ASL and LSR instructions, ROL doesn't change the actual bits themselves; it changes only their positions within the number. For example, if we write a program which has eight consecutive ROL instructions, we return to the same number with which we began. Using eight consecutive ASL or LSR instructions would give us an answer of zero, since for each of the eight instructions, one more bit is set to zero.

Each bit of the original number is moved one position to the left following a ROL instruction, so if the Carry bit is initially zero, the original number is doubled each time this instruction is used. The same cautions discussed in the section on the ASL instruction also apply to the use of the ROL instruction.

EFFECTS ON THE PROCESSOR STATUS REGISTER

The ROL instruction sets the Carry bit equal to the value of the most significant bit of the original number. If the answer is equal to zero, the Zero bit will be set; otherwise, it will be reset. Finally, if the answer is greater than 127 (which will happen if bit 6 of the original number is a 1), the Negative flag will be set; otherwise, it will be reset.

The ROL instruction uses the same five addressing modes as do the ASL and LSR instructions:

 Mode Instruction Cycles Bytes Meaning Absolute ROL \$3420 6 3 ROL contents of memory \$3420 Zero Page ROL \$F6 5 2 ROL contents of memory \$F6 Zero Page,X ROL \$F6,X 6 2 ROL contents of memory \$F6 + X Absolute,X ROL \$3420,X 7 3 ROL contents of memory \$3420 + X Accumulator ROL A 2 1 ROL contents of accumulator

ROR Rotate Right

THE INSTRUCTION

As you might guess, the ROR and ROL instructions are exact opposites. ROR performs a rotation to the right, dividing a number by 2 if the Carry bit was initially zero. Apply the same cautions that were discussed for the LSR instruction. ROR can be represented pictorially as follows:

C         76543210
before: 1  ⇒   01101100
76543210  C
after:                10110110   0

Note that the rotation of the bits is to the right and the original Carry bit is transferred into bit 7 of the answer. Bit 0 of the starting number is transferred to the Carry bit following the operation.

EFFECTS ON THE PROCESSOR STATUS REGISTER

The Carry bit will be set to the value of the least significant bit (bit 0) of the number being rotated. If the resulting number is equal to zero, the Zero flag will be set; otherwise, it will be reset. If the resulting number is greater than 127 (which will happen if the Carry bit had been set prior to the ROR), the Negative flag will be set; otherwise, it will be reset.

The five addressing modes available for the ROR instruction are the same as those just discussed for the ROL instruction and are outlined below:

 Mode Instruction Cycles Bytes Meaning Absolute ROR \$3420 6 3 ROR contents of memory \$3420 Zero Page ROR \$F6 5 2 ROR contents of memory \$F6 Zero Page,X ROR \$F6,X 6 2 ROR contents of memory \$F6 + X Absolute,X ROR \$3420,X 7 3 ROR contents of memory \$3420 + X Accumulator ROR \$3420,Y 2 1 ROR contents of memory \$3420 + Y

RTI Return from Interrupt

THE INSTRUCTION

As we have already discussed briefly, the ATARI makes frequent use of interrupt routines. These divert programs from their normal flow to a new section which performs a particular funtion, and then return the program flow back to the point at which the interrupt occurred. The RTI instruction is provided in the 6502 instruction set to accomplish this return to normal flow.

When an interrupt occurs, the 6502 transfers the contents of the processor status register and the program counter onto the stack. When an RTI instruction is encountered, the microprocessor restores these registers from the stack, thus returning to the exact state of the 6502 prior to the interrupt and allowing program flow to resume.

EFFECTS ON THE PROCESSOR STATUS REGISTER

All flags in the processor status register may be changed by the RTI instruction, since the entire register is renewed by pulling the original value off the stack and returning it here.

The RTI instruction uses only the Implied mode of addressing, requiring 1 byte and 6 machine cycles to execute.

RTS Return from Subroutine

THE INSTRUCTION

The RTS instruction in assembly language programming is analogous to the RETURN command of BASIC: it returns to the next statement following the jump to the subroutine. The instruction causes the program counter to be reloaded with the return address, which is taken from the stack where it was placed by the JSR command. In the discussions of the PHA and PHP instructions, we noted the problem which can arise if other numbers have inadvertently been placed on the stack: when the return address is taken, it is wrong and the program dies.

EFFECTS ON THE PROCESSOR STATUS REGISTER

None.

The RTS instruction uses only the Implied addressing mode, requiring only 1 byte of memory and 6 machine cycles to execute.

SBC Subtract with Carry

THE INSTRUCTION

SBC is the only subtraction instruction of the 6502. It allows you to determine the difference between two numbers by loading the first into the accumulator and subtracting the second. For instance, if we want to perform the subtraction

8 - 6 = ?

we can write the following assembly language program to do so:

LDA #8
SBC #6

The answer, 2, remains in the accumulator until needed.

In decimal subtraction, we learned in school that if we don't have a sufficiently large number in the ones column to perform the subtraction, we can borrow 1 ten from the tens column, convert it to 10 ones, add this to the number in the ones column, and perform the subtraction. For instance, when we subtract

24 - 9 = ?

we know that we cannot subtract 9 from 4. We borrow 1 ten from the tens column, which becomes 10 ones, and add this to the 4 we began with, giving us 14 ones. Now we can subtract 9 from 14, leaving 5 in the ones column and obtain the correct answer, 15.

The 6502 performs subtraction in the same way, but it borrows from the Carry bit. For this reason, we must always be certain that the Carry bit is set (equal to 1) before doing a subtraction so that if we need to borrow, we'll have something to borrow. We can be sure that the Carry bit is set by using the SEC instruction which sets the Carry bit. Now, to do a more complicated subtraction, the assembly language code might look like this:

SEC     ; Be sure C is set
LDA #24 ; 1st number
SBC #26 ; 2nd number
?       ; Answer now in accumulator

What is the answer at the "?"? We set the Carry bit before we started, and it's obvious that we needed to borrow before we could perform the subtraction. Therefore, it's apparent that the Carry bit following this subtraction will be zero. When it is used for borrowing, the Carry bit has a value of 256; we began with the number 256 + 24 = 280 and we subtracted 26, leaving an answer of 254.

Using the SBC instruction, we can subtract any number from another. Note that here we have confined our examples to numbers which can be expressed in a single byte. Double-precision arithmetic was used in several examples in Chapters 7 to 10.

EFFECTS ON THE PROCESSOR STATUS REGISTER

As described above, the Carry bit will be reset if a borrow is necessary to perform the subtraction. The Negative flag is set if the answer is greater than 127; otherwise, it is reset. The Zero flag is set if the answer is equal to zero; otherwise, it is reset. The Overflow flag is set when the answer is larger than plus or minus 127; otherwise, it is reset.

The SBC instruction uses the same eight addressing modes as the LDA instruction. Please refer to Chapter 5 for details of these modes.

 Mode Instruction Cycles Bytes Meaning Immediate SBC #2 2 2 A - #2 Absolute SBC \$3420 4 3 A - contents of memory \$3420 Zero Page SBC \$F6 3 2 A - contents of memory \$F6 Zero Page,X SBC \$F6,X 4 2 A - contents of memory \$F6 +X Absolute,X SBC \$3420,X 4 3 A - contents of memory \$3420 + X Absolute,Y SBC \$3420,Y 4 3 A - contents of memory \$3420 + Y Indexed Indirect SBC (\$F6,X) 6 2 A - contents of address at \$F6 + X Indirect Indexed SBC (\$F6),Y 5 2 A - contents of (address at \$F6) + offset Y

SEC Set the Carry Bit

THE INSTRUCTION

This instruction is used whenever it is necessary to set the Carry bit to 1. The primary use of SEC is prior to subtractions, as described for SBC. Another use of SEC is prior to a rotate command, when you want to force the Carry bit to 1 before the rotation.

EFFECTS ON THE PROCESSOR STATUS REGISTER

The only effect of the SEC instruction on the processor status register is to set the Carry bit unconditionally.

The only addressing mode for the SEC instruction is the Implied mode. It is a 1-byte instruction and requires 2 machine cycles to execute.

SED Set the Decimal Mode

THE INSTRUCTION

As discussed in the sections on the CLD and ADC instructions, the 6502 can operate either in the binary or the decimal mode. To set it in the binary mode, we use the CLD instruction, and to set it in the decimal mode, we use the SED instruction. Note that all additions and subtractions following SED will be in the decimal mode, until cleared by the CLD instruction.

EFFECTS ON THE PROCESSOR STATUS REGISTER

The SED instruction unconditionally sets the Decimal flag equal to 1. It has no other effects.

The only addressing mode used by the SED instruction is the Implied mode, using 1 byte of memory and 2 machine cycles to execute.

SEI Set the Interrupt Flag

THE INSTRUCTION

As mentioned previously, setting the interrupt flag will prevent maskable interrupts such as display list and vertical blank interrupts from occurring. There are times when we would like to write our own interrupt handler, a program which the computer will execute whenever an interrupt occurs. Before we direct the computer to our routine, it's good programming practice to set the interrupt flag, direct the 6502 to our routine's location by setting the appropriate vector (discussed in Chapter 8), and then clear the interrupt flag to resume normal operations. This is how we prevent an interrupt from occurring while we are changing the address of the interrupt vector. If such an interrupt occurred when we were halfway through the change, the computer would no doubt crash. The SEI instruction prevents this from happening.

EFFECTS ON THE PROCESSOR STATUS REGISTER

The only effect of the SEI instruction is to unconditionally set the Interrupt flag to 1.

Like the two previous instructions, the SEI instruction uses only the Implied addressing mode, and takes 1 byte of memory and 2 machine cycles to execute.

STA Store the Accumulator in Memory

THE INSTRUCTION

Just as the LDA instruction can load the accumulator from any memory location, the STA instruction can store whatever value is in the accumulator into any memory location. Note that this instruction does not affect the value stored in the accumulator. It just copies this value into some memory location for storage. We know how to move a value from one place in memory to another, as follows:

LDA \$2468 ; Load from location 1
STA \$1357 ; And store in location 2

In fact, we can now get fairly sophisticated and transfer a whole block of memory from one place to another:

LDY #\$50     ; Set up number of bytes to move
LOOP LDA \$5678,Y  ; Get first byte from \$56C8
STA \$4567,Y  ; Deposit it in \$45B7
DEY          ; Decrement counter
BNE LOOP     ; If counter > 0 then loop
.            ; Gets here only when done

Look particularly at the LDA and STA instructions. Both use the Absolute,Y addressing mode, which allows Y to act not only as the loop counter, but also as the offset from the base addresses from which to load, and to which to transfer. The first byte transferred by this routine is the highest byte of the block, and the routine moves down through memory – until the last byte transferred is the one from \$5678 to \$4567. After that transfer, when we decrement the Y register again, it will equal zero. Therefore, the branch back to LOOP will not be taken, since we loop to LOOP only if the Zero flag is not equal to 1 at this point.

Let's look briefly at the speed of such a routine. We have moved 80 bytes of memory (remember, #\$50 = #80). First we loaded the Y register using the Immediate mode, which takes 2 machine cycles. Then we go through the loop 80 times. Each loop consists of one LDA and one STA, both in the Absolute,Y addressing mode, one DEY, and one BNE instruction. If we add the cycles for the loop, we get

LDA  =   4
STA  =   4
DEY  =   2
BNE  =   2

Total  = 12

Multiplying by 80 loops yields 960 machine cycles, and adding the 2 for the LDY instruction gives a total time of 962 machine cycles. Since each cycle in your ATARI takes 0.56 microseconds, the total elapsed time to move 80 bytes of memory from one location to another was 538.72 microseconds. In BASIC, using a program similar to this

10 FOR I=1 TO 80
30 NEXT I

to accomplish the same end requires 1.25 seconds! Using a machine language routine to accomplish this task increased the speed 2329fold! Other examples of transferring blocks of memory can be found in Chapter 7.

EFFECTS ON THE PROCESSOR STATUS REGISTER

None.

The STA instruction uses seven of the eight addressing modes available to its counterpart, the LDA instruction. Addressing modes are fully explained in Chapter 5 and are merely outlined here:

 Mode Instruction Cycles Bytes Meaning Absolute STA \$3420 4 3 STA A into memory \$3420 Zero Page STA \$F6 3 2 STA A into memory \$F6 Zero Page,X STA \$F6,X 4 2 STA A into memory \$F6 + X Absolute,X STA \$3420,X 4 3 STA A into memory \$3420 + X Absolute,Y STA \$3420,Y 4 3 STA A into memory \$3420 + Y Indexed Indirect STA (\$F6,X) 6 2 STA A into address at \$F6 + X Indirect Indexed STA (\$F6),Y 5 2 STA A into (address at \$F6) + offset Y

STX Store the X Register

THE INSTRUCTION

The STX instruction may be used exactly like the STA instruction, except that the value in the X register, rather than in the accumulator, is stored in memory.

EFFECTS ON THE PROCESSOR STATUS REGISTER

None.

The STX instruction uses three addressing modes as outlined below:

 Mode Instruction Cycles Bytes Meaning Absolute STX \$3420 4 3 STX into memory \$3420 Zero Page STX \$F6 3 2 STX into memory \$F6 Zero Page,Y STX \$F6,Y 4 2 STX into memory \$F6 + Y

STY Store the Y Register

THE INSTRUCTION

STY, just like the STA and STX instructions, stores the value contained in a register (this time, the Y register) into memory.

EFFECTS ON THE PROCESSOR STATUS REGISTER

None.

The three addressing modes used with the STY instruction are outlined below:

 Mode Instruction Cycles Bytes Meaning Absolute STY \$3420 4 3 STY into memory \$3420 Zero Page STY \$F6 3 2 STY into memory \$F6 Zero Page,X STY \$F6,X 4 2 STY into memory \$F6 + X

TAX Transfer Accumulator to the X Register

THE INSTRUCTION

TAX is a transfer instruction which copies the value stored in the accumulator into the X register, leaving the accumulator unchanged.

EFFECTS ON THE PROCESSOR STATUS REGISTER

If the number transfered is greater than 127, the Negative flag is set; otherwise, it is reset. If the number transfered is equal to zero, the Zero flag is set; otherwise, it is reset.

Only the Implied mode is available for the transfer instructions, requiring 1 byte of memory and 2 machine cycles.

TAY Transfer Accumulator to the Y Register

THE INSTRUCTION

This instruction transfers the value in the accumulator into the Y register.

EFFECTS ON THE PROCESSOR STATUS REGISTER

If the number in the accumulator is greater than 127, the Negative flag will be set; otherwise, it will be reset. If the number is equal to zero, the Zero flag will be set; otherwise, it will be reset.

Only the Implied mode, which takes 1 byte of memory and 2 machine cycles to execute, is available for the TAY instruction.

TSX Transfer the Stack Pointer to the X Register

THE INSTRUCTION

The transfer instruction TSX copies the stack pointer into the X register, usually prior to storing it for future use.

EFFECTS ON THE PROCESSOR STATUS REGISTER

If the stack pointer was greater than 127 (and it usually is), the Negative flag will be set; otherwise, it will be reset. If the stack pointer was equal to zero (almost never), then the Zero flag will be set; otherwise, it will be reset.

The TSX instruction uses only the Implied mode, taking 1 byte of memory and 2 machine cycles.

TXA Transfer the X Register to the Accumulator

THE INSTRUCTION

This is the counterpart to the TAX instruction and transfers a value from the X register to the accumulator without changing the value stored in the X register.

EFFECTS ON THE PROCESSOR STATUS REGISTER

The TXA instruction sets the Negative flag if the transfered number was greater than 127; otherwise, it resets it. If the number transfered was equal to zero, the Zero flag will be set; otherwise, it will be reset.

The only addressing mode for the TXA instruction is the Implied mode, using 1 byte of memory and 2 machine cycles to execute.

TXS Transfer the X Register to the Stack Pointer

THE INSTRUCTION

This instruction is most frequently used when you wish to set the stack pointer to some predetermined number. Use TXS with extreme caution! You know what can happen when the stack is messed up. Nothing can upset the stack more than the incorrect use of the TXS instruction, so be very careful in its use.

EFFECTS ON THE PROCESSOR STATUS REGISTER

The TXS instruction has no effect on any of the flags in the processor status register.

The only addressing mode for the TXS instruction is the Implied mode, using 1 byte of memory and 2 machine cycles to execute.

TYA Transfer the Y Register to the Accumulator

THE INSTRUCTION

TYA transfers the number stored in the Y register into the accumulator, leaving a copy of it in the Y register. It is the counterpart of the TAY instruction already discussed.

EFFECTS ON THE PROCESSOR STATUS REGISTER

If the number transfered is greater than 127, the Negative flag is set; otherwise, it is reset. If the number is equal to zero, the Zero flag is set; otherwise, it is reset.

Like the other transfer instructions, the TYA instruction uses only the Implied addressing mode, requiring 1 byte of memory and 2 machine cycles to execute.